Speaker
Jan Reineke
Jan Reineke is a professor of computer science at Saarland University. Before joining Saarland University in 2012, he has been a postdoctoral scholar at UC Berkeley in the Ptolemy group from 2009 to 2011. He completed his MSc and PhD in Computer Science at Saarland University in 2005 and 2008, respectively, and his BSc in Computing Science at the University of Oldenburg in 2003.
His research centers around problems at the boundary between hardware and software.
In the area of real-time systems, he is particularly interested in principles for the design of timing-predictable hardware and in precise and efficient timing-analysis techniques for multi-core architectures. His recent results include the design of the first provably timing-predictable pipelined processor design (RTSS 2018) and the first exact analyses for LRU caches (CAV 2017, POPL 2019, RTSS 2019).
Another focus of his work are security vulnerabilities of hardware-software systems. Recent results include the development of automatic techniques to detect information leaks introduced by speculative execution (Spectector, S&P 2020), techniques to quantify the information leakage through cache side channels (ACM TISSEC 2015), and automatic methods to obtain highly detailed performance models for modern microarchitectures (uops.info, ASPLOS 2019).
In 2012, he was selected as an Intel Early Career Faculty Honor Program awardee. He was the PC chair of EMSOFT 2014, the International Conference on Embedded Software, a Topic co-chair at DATE 2016 and the PC chair of WCET 2017, the International Workshop on Worst-Case Execution Time Analysis. His papers have been awarded 9 outstanding paper awards and two best-paper nominations, most recently at DATE (2024), CCS (2023), RTSS (2023, 2019, 2018), Oakland (2021), and ECRTS (2017). In 2021, he has been awarded an ERC Advanced Grant.